1. Field of the Invention
The present invention relates to a non-volatile memory device.
2. Description of the Related Art
FIG. 1 is a circuit diagram of a non-volatile memory device according to the related art. A non-volatile memory device, e.g., a non-volatile static random access memory (nvSRAM), may include an SRAM latch 50 having transistors 51 and 52, pass gates 40 and 41 reading/writing a high/low state formed in the SRAM latch 50, a silicon-oxide-nitride-oxide-silicon (SONOS) transistor 20 for storing the high/low state of the SRAM latch 50 when the power is turned off, and pass and recall transistors 30 and 10 controlling read, program, and erase operations of the SONOS transistor 20.
FIG. 2 is a cross-sectional view of a non-volatile memory device according to the related art. An impurity diffusion region 13 may be formed between a SONOS electrode 22 of the SONOS transistor 20 and a recall electrode 15 of the recall transistor 10. Another impurity diffusion region 33 may be formed between the SONOS electrode 22 and a pass electrode 35 of the pass transistor 30. Also, impurity diffusion regions 11 and 31 may be formed adjacent to the recall electrode 15 and the pass electrode 35 to be symmetric to the former impurity diffusion regions 13 and 33, respectively.
When reading information stored in the SONOS transistor of the above-configured non-volatile memory device, a high-state voltage is applied to the recall transistor 10, the pass transistor 30, and a Vcc node 101 by a logic circuit while the SONOS transistor 20 is grounded.
In doing so, both the recall and pass transistors 10 and 30 are turned on by the high-state voltage. And, the left SONOS transistor (e.g., in erase mode) 20 and a right SONOS transistor (e.g., in program mode) 21 selectively apply the voltage applied to the Vcc node 101 according to their turn-on or turn-off states. Hence, left and right sides of the SRAM latch 50 are in high and low states according to the operations of the SONOS transistors 20 and 21, respectively. As a result, the logic circuit is facilitated to read the information stored in the SONOS transistors 20 and 21.
Under the above bias condition, most of the voltage applied to the Vcc node 101, as shown in FIG. 2, is transferred to the impurity diffusion region 13 of the SONOS electrode 22. A depletion area 14 then extends toward a channel area CA of the SONOS electrode 22 by the transferred voltage.
In doing so, since the channel area CA of the SONOS electrode 22 is counter-doped to lower its threshold voltage, the depletion area 14 having extended to the channel area of the SONOS electrode 22 may be merged with another depletion area 34 unless a separate management is performed thereon.
If the depletion area 14 merges with another depletion area 34, the SONOS electrode 22 completely loses its control over its channel area CA so that current always flows to the Vcc node 101 to a Vs node 102 regardless of the erase or program mode of the SONOS electrode 22. Consequently, the nvSRAM is unable to normally perform its function.